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» Sequential Verification of Serializability
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ICCD
1996
IEEE
170views Hardware» more  ICCD 1996»
13 years 11 months ago
Boolean Function Representation Based on Disjoint-Support Decompositions
The Multi-Level Decomposition Diagrams (MLDDs) of this paper are a canonical representation of Boolean functions expliciting disjoint-support decompositions. MLDDs allow the reduc...
Valeria Bertacco, Maurizio Damiani
FMCAD
2000
Springer
13 years 11 months ago
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
David A. Basin, Stefan Friedrich, Sebastian Mö...
AMAST
2008
Springer
13 years 9 months ago
Vx86: x86 Assembler Simulated in C Powered by Automated Theorem Proving
Abstract. Vx86 is the first static analyzer for sequential Intel x86 assembler code using automated deductive verification. It proves the correctness of assembler code against func...
Stefan Maus, Michal Moskal, Wolfram Schulte
BIOSIG
2003
89views Biometrics» more  BIOSIG 2003»
13 years 8 months ago
How to Test the Performance of Speech Verifiers and Statistical Evaluation
Abstract: Biometric identification and verification technologies, in the past, have promised high performance levels. Such performance statements lead to the assumption, that these...
Jörg Tacke, Andreas Wolf
ENTCS
2002
78views more  ENTCS 2002»
13 years 7 months ago
Slicing Synchronous Reactive Programs
This paper extends the well-known technique of slicing to synchronous reactive programs. Synchronous languages exemplified by Esterel, Lustre, Signal and Argos, novel model of exe...
Vinod Ganapathy, S. Ramesh