This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulat...
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, R...