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HPCA
2012
IEEE
12 years 4 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
PAAPP
2002
76views more  PAAPP 2002»
13 years 8 months ago
Performance of PDE solvers on a self-optimizing NUMA architecture
Abstract. The performance of shared-memory (OpenMP) implementations of three different PDE solver kernels representing finite difference methods, finite volume methods, and spectra...
Sverker Holmgren, Markus Nordén, Jarmo Rant...
IPPS
1999
IEEE
14 years 1 months ago
Visualization and Performance Prediction of Multithreaded Solaris Programs by Tracing Kernel Threads
Efficient performance tuning of parallel programs is often hard. We present a performance prediction and visualization tool called VPPB. Based on a monitored uni-processor executi...
Magnus Broberg, Lars Lundberg, Håkan Grahn
HPCA
1998
IEEE
14 years 1 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
SC
2005
ACM
14 years 2 months ago
Performance Modeling and Tuning Strategies of Mixed Mode Collective Communications
On SMP clusters, mixed mode collective MPI communications, which use shared memory communications within SMP nodes and point-to-point communications between SMP nodes, are more eï...
Meng-Shiou Wu, Ricky A. Kendall, Kyle Wright, Zhao...