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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 12 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
IPPS
2009
IEEE
14 years 2 months ago
Performance evaluation of gang scheduling in a two-cluster system with migrations
Gang scheduling is considered to be a highly effective task scheduling policy for distributed systems. In this paper we present a migration scheme which reduces the fragmentation ...
Zafeirios C. Papazachos, Helen D. Karatza
EUROPAR
2009
Springer
13 years 5 months ago
Argument Controlled Profiling
Profiling tools relate measurements to code context such as function names in order to guide code optimization. For a more detailed analysis, call path or phase-based profiling enh...
Tilman Küstner, Josef Weidendorfer, Tobias We...
PDP
2008
IEEE
14 years 2 months ago
Internet-Scale Simulations of a Peer Selection Algorithm
The match between a peer-to-peer overlay and the physical Internet infrastructure is a constant issue. Time-constrained peer-to-peer applications such as live streaming systems ar...
Ali Boudani, Yiping Chen, Gilles Straub, Gwendal S...
IPPS
1994
IEEE
13 years 12 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...