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» Simulation based deadlock analysis for system level designs
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PACS
2000
Springer
118views Hardware» more  PACS 2000»
14 years 13 days ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
MSWIM
2005
ACM
14 years 2 months ago
Adapting WLAN MAC parameters to enhance VoIP call capacity
This work describes a detailed simulation-based study of the performance of an IEEE 802.11e Medium Access Control (MAC) layer over an IEEE 802.11g Physical (PHY) layer. The study ...
Gráinne Hanley, Seán Murphy, Liam Mu...
ACSD
2010
IEEE
255views Hardware» more  ACSD 2010»
13 years 7 months ago
From POOSL to UPPAAL: Transformation and Quantitative Analysis
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control syst...
Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jac...
CIVR
2005
Springer
125views Image Analysis» more  CIVR 2005»
14 years 2 months ago
Interactive Video Search Using Multilevel Indexing
Large video collections present a unique set of challenges to the search system designer. Text transcripts do not always provide an accurate index to the visual content, and the pe...
John Adcock, Matthew L. Cooper, Andreas Girgensohn...
TVLSI
2008
187views more  TVLSI 2008»
13 years 8 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...