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MTDT
2003
IEEE
124views Hardware» more  MTDT 2003»
14 years 1 months ago
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
Zaid Al-Ars, A. J. van de Goor
WSC
2008
13 years 10 months ago
A new method for bottleneck detection
This paper presents a new method to identify and rank the bottlenecks in a manufacturing system. The proposed method is based on performance related data that are easy to capture,...
Sankar Sengupta, Kanchan Das, Robert P. VanTil
WSC
1998
13 years 9 months ago
Warehouse Design through Dynamic Simulation
Intel's new processors in mid-1997 were a dramatic increased in speed and size over their ancestors. The increased size caused box volume to increase beyond the capacity of t...
Mark Kosfeld
EDBT
2011
ACM
199views Database» more  EDBT 2011»
12 years 11 months ago
Predicting completion times of batch query workloads using interaction-aware models and simulation
A question that database administrators (DBAs) routinely need to answer is how long a batch query workload will take to complete. This question arises, for example, while planning...
Mumtaz Ahmad, Songyun Duan, Ashraf Aboulnaga, Shiv...
ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
13 years 11 months ago
TAPAAL: Editor, Simulator and Verifier of Timed-Arc Petri Nets
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...
Joakim Byg, Kenneth Yrke Jørgensen, Jir&iac...