273 search results - page 19 / 55 » Simulation of hybrid computer architectures: simulators, met... |
GECCO
2005
Springer
14 years 2 months ago
2005
Springer
As high-speed networks have proliferated across the globe, their topologies have become sparser due to the increased capacity of communication media and cost considerations. Relia...
BMCBI
2008
13 years 8 months ago
2008
Background: In individually dye-balanced microarray designs, each biological sample is hybridized on two different slides, once with Cy3 and once with Cy5. While this strategy ens...
DAC
2010
ACM
13 years 9 months ago
2010
ACM
Given the increasing complexity of multi-processor systems-onchip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of ...
IPPS
1992
IEEE
14 years 24 days ago
1992
IEEE
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build th...