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JCP
2008
105views more  JCP 2008»
13 years 7 months ago
Thermal Driven Placement for Island-style MTCMOS FPGAs
Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots...
Javid Jaffari, Mohab Anis
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 29 days ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
LCTRTS
2010
Springer
13 years 5 months ago
Improving both the performance benefits and speed of optimization phase sequence searches
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
Prasad A. Kulkarni, Michael R. Jantz, David B. Wha...
DAC
2009
ACM
14 years 2 days ago
GPU-based parallelization for fast circuit optimization
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
Yifang Liu, Jiang Hu
ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
14 years 4 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young