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HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
CORR
2007
Springer
141views Education» more  CORR 2007»
13 years 7 months ago
A Class of Parallel Tiled Linear Algebra Algorithms for Multicore Architectures
As multicore systems continue to gain ground in the High Performance Computing world, linear algebra algorithms have to be reformulated or new algorithms have to be developed in or...
Alfredo Buttari, Julien Langou, Jakub Kurzak, Jack...
DLT
2003
13 years 9 months ago
Tile Rewriting Grammars
Past proposals for applying to pictures or 2D languages the generative grammar approach do not match in our opinion the elegance and descriptive adequacy that made Context Free gr...
Stefano Crespi-Reghizzi, Matteo Pradella
ERSA
2009
107views Hardware» more  ERSA 2009»
13 years 5 months ago
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
Kenneth C. Rovers, Marcel D. van de Burgwal, Jan K...
JAR
2007
104views more  JAR 2007»
13 years 7 months ago
Student Proof Exercises Using MathsTiles and Isabelle/HOL in an Intelligent Book
The Intelligent Book project aims to improve online education by designing materials that can model the subject matter they teach, in the manner of a Reactive Learning Environment...
William Billingsley, Peter Robinson