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CC
2008
Springer
144views System Software» more  CC 2008»
13 years 9 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
CDES
2008
166views Hardware» more  CDES 2008»
13 years 9 months ago
Scalable Directory Organization for Tiled CMP Architectures
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
Alberto Ros, Manuel E. Acacio, José M. Garc...
CF
2006
ACM
14 years 1 months ago
Tile size selection for low-power tile-based architectures
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...
John Oliver, Ravishankar Rao, Michael Brown, Jenni...
TCS
2008
13 years 7 months ago
Solving NP-complete problems in the tile assembly model
Formalized study of self-assembly has led to the definition of the tile assembly model, a highly distributed parallel model of computation that may be implemented using molecules ...
Yuriy Brun
ICECCS
2010
IEEE
162views Hardware» more  ICECCS 2010»
13 years 7 months ago
A Tile-Based Approach for Self-Assembling Service Compositions
—This paper presents a novel approach to the design of self-adaptive service-oriented applications based on a new model called service tiles. The approach allows designers to dev...
Luca Cavallaro, Elisabetta Di Nitto, Carlo A. Furi...