As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...