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DFT
1999
IEEE
139views VLSI» more  DFT 1999»
13 years 11 months ago
Soft-Error Detection through Software Fault-Tolerance Techniques
The paper describes a systematic approach for automatically introducing data and code redundancy into an existing program written using a high-level language. The transformations ...
Maurizio Rebaudengo, Matteo Sonza Reorda, Marco To...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 1 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
CGO
2009
IEEE
14 years 1 months ago
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
—As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. ...
Jing Yu, María Jesús Garzarán...
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
14 years 6 days ago
The positive effect on IC yield of embedded Fault Tolerance for SEUs
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
André K. Nieuwland, Richard P. Kleihorst
ARCS
2010
Springer
14 years 1 months ago
Exploiting Inactive Rename Slots for Detecting Soft Errors
Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical register mapping for...
Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, M...