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CASES
2009
ACM
14 years 8 days ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
ASPLOS
2008
ACM
13 years 11 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
CASES
2008
ACM
13 years 11 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
WSC
2000
13 years 10 months ago
Dynamic component substitution in web-based simulation
Recent breakthroughs in communication and software engineering has resulted in significant growth of web-based computing. Web-based techniques have been employed for modeling, sim...
Dhananjai Madhava Rao, Philip A. Wilsey
TASE
2008
IEEE
13 years 8 months ago
New Hybrid Optimization Algorithms for Machine Scheduling Problems
Dynamic programming, branch-and-bound, and constraint programming are the standard solution principles for nding optimal solutions to machine scheduling problems. We propose a new ...
Yunpeng Pan, Leyuan Shi