1541 search results - page 31 / 309 » Software Hardware Co-Scheduling for Reconfigurable Computing... |
EH
1999
IEEE
14 years 1 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
ARC
2010
Springer
13 years 9 months ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
IEEEPACT
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper presents the Cameron Project 1 , which aims to provide a high level, algorithmic language and optimizing compiler for the development of image processing applications o...
FCCM
2004
IEEE
14 years 14 days ago
2004
IEEE
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
ECOOP
2008
Springer
13 years 10 months ago
2008
Springer
Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores ar...