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LCTRTS
2009
Springer
15 years 9 months ago
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...
115
Voted
CODES
2006
IEEE
15 years 8 months ago
TLM/network design space exploration for networked embedded systems
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
Nicola Bombieri, Franco Fummi, Davide Quaglia
117
Voted
MSS
2000
IEEE
106views Hardware» more  MSS 2000»
15 years 6 months ago
Disk Subsystem Performance Evaluation: From Disk Drives to Storage Area Networks
Disk subsystems span the range of configuration complexity from single disk drives to large installations of disk arrays. They can be directly attached to individual computer syst...
Thomas Ruwart
PVLDB
2010
139views more  PVLDB 2010»
15 years 27 days ago
Aether: A Scalable Approach to Logging
The shift to multi-core hardware brings new challenges to database systems, as the software parallelism determines performance. Even though database systems traditionally accommod...
Ryan Johnson, Ippokratis Pandis, Radu Stoica, Mano...
149
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CAL
2007
15 years 2 months ago
Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture
—Flash memory solid state disk (SSD) is gaining popularity and replacing hard disk drive (HDD) in mobile computing systems such as ultra mobile PCs (UMPCs) and notebook PCs becau...
Jinhyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong, Hongs...