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» Software debugging, testing, and verification
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AMOST
2005
ACM
14 years 1 months ago
Using information about functions in selecting test cases
We consider the problem of generating a set of test cases from a black box specification. We focus on stress testing, i.e. picking test cases that seem most likely to reveal prog...
Markus Clermont, David Lorge Parnas
VEE
2012
ACM
269views Virtualization» more  VEE 2012»
12 years 3 months ago
SimTester: a controllable and observable testing framework for embedded systems
In software for embedded systems, the frequent use of interrupts for timing, sensing, and I/O processing can cause concurrency faults to occur due to interactions between applicat...
Tingting Yu, Witawas Srisa-an, Gregg Rothermel
BELL
2000
107views more  BELL 2000»
13 years 7 months ago
Automating software feature verification
A significant part of the call processing software for Lucent's new PathStar access server [FSW98] was checked with automated formal verification techniques. The verification...
Gerard J. Holzmann, Margaret H. Smith
SENSYS
2009
ACM
14 years 2 months ago
Macrodebugging: global views of distributed program execution
Creating and debugging programs for wireless embedded networks (WENs) is notoriously difficult. Macroprogramming is an emerging technology that aims to address this by providing ...
Tamim I. Sookoor, Timothy W. Hnat, Pieter Hooimeij...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...