Sciweavers

7404 search results - page 1369 / 1481
» Software performance antipatterns
Sort
View
180
Voted
FMCAD
2006
Springer
15 years 8 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
HPCN
2000
Springer
15 years 8 months ago
An Analytical Model for a Class of Architectures under Master-Slave Paradigm
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
Yasemin Yalçinkaya, Trond Steihaug
ICS
2000
Tsinghua U.
15 years 8 months ago
Push vs. pull: data movement for linked data structures
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetchin...
Chia-Lin Yang, Alvin R. Lebeck
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
15 years 8 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
PARA
1995
Springer
15 years 8 months ago
ScaLAPACK Tutorial
Abstract. ScaLAPACK is a library of high performance linear algebra routines for distributed memory MIMD computers. It is a continuation of the LAPACK project, which designed and p...
Jack Dongarra, Antoine Petitet
« Prev « First page 1369 / 1481 Last » Next »