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ISPASS
2010
IEEE
14 years 2 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
HIPEAC
2007
Springer
14 years 1 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...
CSMR
2010
IEEE
13 years 2 months ago
A Heuristic-Based Approach to Identify Concepts in Execution Traces
Abstract--Concept or feature identification, i.e., the identification of the source code fragments implementing a particular feature, is a crucial task during software understandin...
Fatemeh Asadi, Massimiliano Di Penta, Giuliano Ant...
MM
2009
ACM
131views Multimedia» more  MM 2009»
14 years 2 months ago
Towards characterizing user interaction with progressively transmitted 3D meshes
We collected traces of how 37 users interacted with 9 progressively streamed and rendered 3D meshes. We analyze the traces and discuss the insights that we learned in relation to ...
Ransi Nilaksha De Silva, Wei Cheng, Dan Liu, Wei T...
IMECS
2007
13 years 9 months ago
A Hybrid Markov Model for Accurate Memory Reference Generation
—Workload characterisation and generation is becoming an increasingly important area as hardware and application complexities continue to advance. In this paper, we introduce a c...
Rahman Hassan, Antony Harris