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HIPEAC
2011
Springer
12 years 9 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
DIGRA
2005
Springer
14 years 3 months ago
The Pervasive Interface; Tracing the Magic Circle
This paper is an addition to the discourse surrounding interface theory and pervasive games. A buzzword by nature, the term ´interface´ needs to be investigated and redefined in...
Eva Nieuwdorp
RT
2004
Springer
14 years 3 months ago
An Irradiance Atlas for Global Illumination in Complex Production Scenes
We introduce a tiled 3D MIP map representation of global illumination data. The representation is an adaptive, sparse octree with a “brick” at each octree node; each brick con...
Per H. Christensen, Dana Batali
SC
1991
ACM
14 years 1 months ago
Input/output behavior of supercomputing applications
: This paper describes the collection and analysis of supercomputer I/O traces and their use in a collection of buffering and caching simulations. This serves two purposes. First, ...
Ethan L. Miller, Randy H. Katz
PARA
2004
Springer
14 years 3 months ago
A Cache-Aware Algorithm for PDEs on Hierarchical Data Structures
A big challenge in implementing up to date simulation software for various applications is to bring together highly efficient mathematical methods on the one hand side and an ef...
Frank Günther, Miriam Mehl, Markus Pögl,...