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» Software transactional memory for multicore embedded systems
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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
14 years 1 months ago
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...
ASPDAC
2008
ACM
107views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata
The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded Software Metadata inform...
Alexandros Bartzas, Miguel Peón Quiró...
FCCM
2007
IEEE
108views VLSI» more  FCCM 2007»
14 years 1 months ago
Configurable Transactional Memory
Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programmi...
Christoforos Kachris, Chidamber Kulkarni
VMCAI
2009
Springer
14 years 2 months ago
An Abort-Aware Model of Transactional Programming
There has been a lot of recent research on transaction-based concurrent programming, aimed at offering an easier concurrent programming paradigm that enables programmers to better...
Kousha Etessami, Patrice Godefroid