311 search results - page 15 / 63 » Software-Controlled Multithreading Using Informing Memory Op... |
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
IPPS
1998
IEEE
14 years 4 hour ago
1998
IEEE
We have built an eight node SMP cluster called COMPaS (Cluster Of Multi-Processor Systems), each node of which is a quadprocessor Pentium Pro PC. We have designed and implemented a...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
CCGRID
2001
IEEE
13 years 11 months ago
2001
IEEE
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of high performance of VIA, the previous MPI implementati...
AMTA
2004
Springer
14 years 1 months ago
2004
Springer
We describe the use of a translation memory in the context of a reconstruction of a landmark application of machine translation, the Canadian English to French weather report trans...