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ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
13 years 8 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
PDP
2010
IEEE
16 years 21 days ago
Lessons Learnt Porting Parallelisation Techniques for Irregular Codes to NUMA Systems
—This work presents a study undertaken to characterise the behaviour of some parallelisation techniques for irregular codes, previously developed for SMP architectures, on a seve...
Juan Angel Lorenzo, Juan Carlos Pichel, David LaFr...
IPPS
2000
IEEE
15 years 10 months ago
A Mechanism for Speculative Memory Accesses Following Synchronizing Operations
In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following ...
Takayuki Sato, Kazuhiko Ohno, Hiroshi Nakashima
SC
2004
ACM
15 years 11 months ago
Predicting and Evaluating Distributed Communication Performance
–Application of hardware-parameterized models to distributed systems can result in omission of key bottlenecks such as the full cost of inter- and intra-node communication in a c...
Kirk W. Cameron, Rong Ge
ICPP
1994
IEEE
15 years 10 months ago
Cachier: A Tool for Automatically Inserting CICO Annotations
Shared memory in a parallel computer provides prowith the valuable abstraction of a shared address space--through which any part of a computation can access any datum. Although un...
Trishul M. Chilimbi, James R. Larus