230 search results - page 31 / 46 » Software-Extended Coherent Shared Memory: Performance and Co... |
IEEEPACT
1998
IEEE
14 years 2 months ago
1998
IEEE
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
SPAA
2010
ACM
14 years 2 months ago
2010
ACM
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path b...
GLOBECOM
2006
IEEE
14 years 4 months ago
2006
IEEE
— Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The SwitchMemory-Switch...
SC
1991
ACM
14 years 1 months ago
1991
ACM
In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-...