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IPPS
2007
IEEE
14 years 3 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
14 years 1 months ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan
DSN
2006
IEEE
14 years 3 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin
ICDCS
1996
IEEE
14 years 1 months ago
Larchant: Persistence by Reachability in Distributed Shared Memory Through Garbage Collection
We consider a shared store based on distributed shared memory (DSM), supporting persistence by reachability (PBR), a very simple data sharing model for a distributed system. This ...
Paulo Ferreira, Marc Shapiro
SPAA
2010
ACM
14 years 1 months ago
Towards optimizing energy costs of algorithms for shared memory architectures
Energy consumption by computer systems has emerged as an important concern. However, the energy consumed in executing an algorithm cannot be inferred from its performance alone: i...
Vijay Anand Korthikanti, Gul Agha