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ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
14 years 5 months ago
Post-routing redundant via insertion and line end extension with via density consideration
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
TCAD
2008
172views more  TCAD 2008»
13 years 8 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
SIAMREV
2010
174views more  SIAMREV 2010»
13 years 3 months ago
Guaranteed Minimum-Rank Solutions of Linear Matrix Equations via Nuclear Norm Minimization
The affine rank minimization problem consists of finding a matrix of minimum rank that satisfies a given system of linear equality constraints. Such problems have appeared in the ...
Benjamin Recht, Maryam Fazel, Pablo A. Parrilo
SOCIALCOM
2010
13 years 6 months ago
Estimating the Size of Online Social Networks
The huge size of online social networks (OSNs) makes it prohibitively expensive to precisely measure any properties which require the knowledge of the entire graph. To estimate the...
Shaozhi Ye, Shyhtsun Felix Wu
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 2 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...