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IPPS
2006
IEEE
15 years 8 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
CCGRID
2001
IEEE
15 years 6 months ago
xBSP: An Efficient BSP Implementation for clan
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of high performance of VIA, the previous MPI implementati...
Yang-Suk Kee, Soonhoi Ha
145
Voted
EUROPAR
2000
Springer
15 years 6 months ago
Ahnentafel Indexing into Morton-Ordered Arrays, or Matrix Locality for Free
Abstract. Definitions for the uniform representation of d-dimensional matrices serially in Morton-order (or Z-order) support both their use with cartesian indices, and their divide...
David S. Wise
132
Voted
GRID
2008
Springer
15 years 3 months ago
Dynamic scheduling for heterogeneous Desktop Grids
Desktop Grids have emerged as an important methodology to harness the idle cycles of millions of participant desktop PCs over the Internet. However, to effectively utilize the res...
Issam Al-Azzoni, Douglas G. Down
GLOBECOM
2006
IEEE
15 years 8 months ago
Sensor Localization from WLS Optimization with Closed-form Gradient and Hessian
— A non-parametric, low-complexity algorithm for accurate and simultaneous localization of multiple sensors from scarce and imperfect ranging information is proposed. The techniq...
Giuseppe Destino, Giuseppe Thadeu Freitas de Abreu