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DAC
2007
ACM
15 years 10 months ago
Design for Verification in System-level Models and RTL
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
Anmol Mathur, Venkat Krishnaswamy
CSDA
2008
108views more  CSDA 2008»
15 years 6 months ago
The random Tukey depth
The computation of the Tukey depth, also called halfspace depth, is very demanding, even in low dimensional spaces, because it requires that all possible one-dimensional projectio...
J. A. Cuesta-Albertos, A. Nieto-Reyes
CG
2006
Springer
15 years 6 months ago
Connectivity preserving digitization of blurred binary images in 2D and 3D
Connectivity and neighborhood are fundamental topological properties of objects in pictures. Since the input for any image analysis algorithm is a digital image, which does not ne...
Peer Stelldinger, Ullrich Köthe
SIGMETRICS
2002
ACM
15 years 5 months ago
Full-system timing-first simulation
Computer system designers often evaluate future design alternatives with detailed simulators that strive for functional fidelity (to execute relevant workloads) and performance fi...
Carl J. Mauer, Mark D. Hill, David A. Wood
ATS
1997
IEEE
89views Hardware» more  ATS 1997»
15 years 10 months ago
Guaranteeing Testability in Re-encoding for Low Power
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Mau...