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MEMOCODE
2003
IEEE
14 years 20 days ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
IFIP
2001
Springer
13 years 12 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
FMSD
2006
140views more  FMSD 2006»
13 years 7 months ago
Dealing with practical limitations of distributed timed model checking for timed automata
Two base algorithms are known for reachability verification over timed automata. They are called forward and backwards, and traverse the automata edges using either successors or p...
Víctor A. Braberman, Alfredo Olivero, Ferna...
AMAST
2010
Springer
13 years 2 months ago
Integrating Maude into Hets
Maude modules can be understood as models that can be formally analyzed and verified with respect to different properties expressing various formal requirements. However, Maude lac...
Mihai Codescu, Till Mossakowski, Adrián Rie...
SP
1997
IEEE
134views Security Privacy» more  SP 1997»
13 years 11 months ago
A Logical Language for Expressing Authorizations
A major drawback of existing access control systems is that they have all been developed with a specific access control policy in mind. This means that all protection requirement...
Sushil Jajodia, Pierangela Samarati, V. S. Subrahm...