354 search results - page 7 / 71 » Sorting networks on FPGAs |
ERSA
2006
14 years 8 days ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
FPGA
2009
ACM
14 years 5 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
COMBINATORICS
1998
13 years 10 months ago
1998
Let α and β be a partition of {1, . . . , n} into two blocks. A merging network is a network of comparators which allows as input arbitrary real numbers and has the property tha...
IPPS
1998
IEEE
14 years 3 months ago
1998
IEEE
Abstract. We give a high-level description of some fundamental randomized and deterministic techniques for routing and sorting on xedconnection networks such as meshes, hypercubes ...
ICPP
1995
IEEE
14 years 2 months ago
1995
IEEE
If G is a connected graph with N nodes, its r dimensional product contains Nr nodes. We present an algorithm which sorts Nr keys stored in the rdimensional product of any graph G ...