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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 1 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
DAC
2007
ACM
13 years 11 months ago
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices
The number of features that are supported in modern multimedia devices is increasing faster than ever. Estimating the performance of such applications when they are running on sha...
Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. ...
CLUSTER
2006
IEEE
14 years 1 months ago
A Performance Prediction Methodology for Data-dependent Parallel Applications
The increase in the use of parallel distributed architectures in order to solve large-scale scientific problems has generated the need for performance prediction for both determi...
Paula Cecilia Fritzsche, Concepció Roig, An...
SNPD
2003
13 years 9 months ago
Pattern Matching of Parallel Values in Bulk Synchronous Parallel ML
We have designed a functional data-parallel language called BSML for programming bulk-synchronous parallel (BSP) algorithms in so-called direct mode. In a directmode BSP algorithm...
Frédéric Gava, Frédéri...
COOPIS
2004
IEEE
13 years 11 months ago
TRAP/J: Transparent Generation of Adaptable Java Programs
This paper describes TRAP/J, a software tool that enables new adaptable behavior to be added to existing Java applications transparently (that is, without modifying the application...
Seyed Masoud Sadjadi, Philip K. McKinley, Betty H....