104 search results - page 13 / 21 » Source-to-Source Architecture Transformation for Performance... |
ICPPW
2005
IEEE
14 years 1 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
ICPPW
2006
IEEE
14 years 1 months ago
2006
IEEE
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
SAMOS
2004
Springer
14 years 24 days ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
IPSN
2009
Springer
14 years 2 months ago
2009
Springer
As the diversity of sensornet use cases increases, the combinations of environments and applications that will coexist will make custom engineering increasingly impractical. We in...