317 search results - page 46 / 64 » Space Reductions for Model Checking Quasi-Cyclic Systems |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
FDL
2006
IEEE
14 years 1 months ago
2006
IEEE
Reusing IP-cores to construct system models facilitated by automated generation of glue-logic, and automated composability checks can help designers to create efficient simulation...
AGP
2010
IEEE
13 years 12 months ago
2010
IEEE
We present an overview of the program transformation techniques which have been proposed over the past twenty-five years in the context of logic programming. We consider the appro...
ACSD
2006
IEEE
14 years 1 months ago
2006
IEEE
A schedule of a Petri Net (PN) represents a set of firing sequences that can be infinitely repeated within a bounded state space, regardless of the outcomes of the nondeterminis...
KBSE
2007
IEEE
14 years 2 months ago
2007
IEEE
Concurrent programs are difficult to debug and verify because of the nondeterministic nature of concurrent executions. A particular concurrency-related bug may only show up under ...