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TPHOL
2005
IEEE
14 years 3 months ago
From PSL to LTL: A Formal Validation in HOL
Using the HOL theorem prover, we proved the correctness of a translation from a subset of Accellera’s property specification language PSL to linear temporal logic LTL. Moreover,...
Thomas Tuerk, Klaus Schneider
CAV
2003
Springer
156views Hardware» more  CAV 2003»
14 years 3 months ago
Abstraction and BDDs Complement SAT-Based BMC in DiVer
ion and BDDs Complement SAT-based BMC in DiVer Aarti Gupta1, Malay Ganai1 , Chao Wang2, Zijiang Yang1, Pranav Ashar1 1 NEC Laboratories America, Princeton, NJ, U.S.A. 2 University ...
Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Ya...
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
14 years 1 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
PUK
2000
13 years 11 months ago
Heuristic Search Planning with BDDs
Abstract. In this paper we study traditional and enhanced BDDbased exploration procedures capable of handling large planning problems. On the one hand, reachability analysis and mo...
Stefan Edelkamp
QEST
2007
IEEE
14 years 4 months ago
Symbolic Bisimulations for Probabilistic Systems
The paper introduces symbolic bisimulations for a simple probabilistic π-calculus to overcome the infinite branching problem that still exists in checking ground bisimulations b...
Peng Wu 0002, Catuscia Palamidessi, Huimin Lin