Sciweavers

1083 search results - page 105 / 217
» Spatial Memory Streaming
Sort
View
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 11 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
CHI
2010
ACM
14 years 4 months ago
Now let me see where i was: understanding how lifelogs mediate memory
Lifelogging technologies can capture both mundane and important experiences in our daily lives, resulting in a rich record of the places we visit and the things we see. This study...
Vaiva Kalnikaité, Abigail Sellen, Steve Whi...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 3 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ISPASS
2003
IEEE
14 years 2 months ago
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
John W. Haskins Jr., Kevin Skadron
ICDE
2009
IEEE
148views Database» more  ICDE 2009»
14 years 11 months ago
Probabilistic Inference over RFID Streams in Mobile Environments
Abstract-- Recent innovations in RFID technology are enabling large-scale cost-effective deployments in retail, healthcare, pharmaceuticals and supply chain management. The advent ...
Thanh Tran 0002, Charles Sutton, Richard Cocci, Ya...