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» Specify, Compile, Run: Hardware from PSL
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DSD
2006
IEEE
107views Hardware» more  DSD 2006»
14 years 1 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
14 years 4 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
CASES
2005
ACM
13 years 9 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
CCS
2004
ACM
14 years 28 days ago
Verifying policy-based security for web services
WS-SecurityPolicy is a declarative configuration language for driving web services security mechanisms. We describe a formal sefor WS-SecurityPolicy, and propose a more abstract ...
Karthikeyan Bhargavan, Cédric Fournet, Andr...
ASAP
2006
IEEE
145views Hardware» more  ASAP 2006»
14 years 1 months ago
2D-VLIW: An Architecture Based on the Geometry of Computation
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
Ricardo Santos, Rodolfo Azevedo, Guido Araujo