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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 11 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
ICCD
2008
IEEE
192views Hardware» more  ICCD 2008»
14 years 4 months ago
Energy-aware opcode design
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
OSDI
1994
ACM
13 years 8 months ago
Distributed Filaments: Efficient Fine-Grain Parallelism on a Cluster of Workstations
A fine-grain parallel program is one in which processes are typically small, ranging from a few to a few hundred instructions. Fine-grain parallelism arises naturally in many situ...
Vincent W. Freeh, David K. Lowenthal, Gregory R. A...
CODES
2009
IEEE
14 years 7 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
14 years 29 days ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks