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APCSAC
2007
IEEE
14 years 3 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
ISORC
1998
IEEE
14 years 26 days ago
Checked Transactions in an Asynchronous Message Passing Environment
Traditionally transactions have been singlethreaded. In such an environment the thread terminating the transaction is, by definition, the thread which performed the work. Therefor...
Steve J. Caughey, Mark C. Little, Santosh K. Shriv...
RAID
2009
Springer
14 years 3 months ago
Multi-byte Regular Expression Matching with Speculation
Intrusion prevention systems determine whether incoming traffic matches a database of signatures, where each signature in the database represents an attack or a vulnerability. IPSs...
Daniel Luchaup, Randy Smith, Cristian Estan, Somes...
IEEEPACT
2005
IEEE
14 years 2 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...
IPPS
2010
IEEE
13 years 5 months ago
Runtime checking of serializability in software transactional memory
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...
Arnab Sinha, Sharad Malik