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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
14 years 1 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
RTSS
1992
IEEE
14 years 1 months ago
Allocation of periodic task modules with precedence and deadline constraints in distributed real-time systems
This paper addresses the problem of allocating (assigning and scheduling) periodic task modules to processing nodes in distributed real-time systems subject to task precedence and ...
Chao-Ju Hou, Kang G. Shin
CF
2007
ACM
14 years 1 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
CIKM
2009
Springer
14 years 1 months ago
Efficient itemset generator discovery over a stream sliding window
Mining generator patterns has raised great research interest in recent years. The main purpose of mining itemset generators is that they can form equivalence classes together with...
Chuancong Gao, Jianyong Wang
DOCENG
2007
ACM
14 years 1 months ago
Extracting reusable document components for variable data printing
Variable Data Printing (VDP) has brought new flexibility and dynamism to the printed page. Each printed instance of a specific class of document can now have different degrees of ...
Steven R. Bagley, David F. Brailsford, James A. Ol...