Sciweavers

2020 search results - page 45 / 404
» Speeding up Slicing
Sort
View
HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
HOTI
2005
IEEE
14 years 2 months ago
Addressing Queuing Bottlenecks at High Speeds
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley
VECPAR
2004
Springer
14 years 2 months ago
Message Strip-Mining Heuristics for High Speed Networks
In this work we investigate how the compiler technique of message strip mining performs in practice on contemporary high performance networks. Message strip mining attempts to redu...
Costin Iancu, Parry Husbands, Wei Chen
FPL
2006
Springer
96views Hardware» more  FPL 2006»
14 years 13 days ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
ARCS
2008
Springer
13 years 10 months ago
Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...
Joachim Keinert, Christian Haubelt, Jürgen Te...