1937 search results - page 321 / 388 » Starting B Specifications from Use Cases |
274
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GLVLSI
2011
IEEE
14 years 8 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
169
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HPCA
2009
IEEE
16 years 5 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
142
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ECCV
2006
Springer
16 years 6 months ago
2006
Springer
Abstract. This paper presents a novel approach to unsupervised texture segmentation that relies on a very general nonparametric statistical model of image neighborhoods. The method...
148
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PICS
2003
15 years 5 months ago
2003
To establish a correlation between the system output and the corresponding reflectance, the system characterisation functionDeriving the actual multispectral data from the output o...
129
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ICFP
2006
ACM
16 years 4 months ago
2006
ACM
A transient hardware fault occurs when an energetic particle strikes a transistor, causing it to change state. These faults do not cause permanent damage, but may result in incorr...