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» State of the art in testing components
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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 2 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ECBS
2006
IEEE
203views Hardware» more  ECBS 2006»
13 years 11 months ago
The Feature-Architecture Mapping (FArM) Method for Feature-Oriented Development of Software Product Lines
Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are sca...
Periklis Sochos, Matthias Riebisch, Ilka Philippow
FAC
2008
64views more  FAC 2008»
13 years 7 months ago
Testing a deterministic implementation against a non-controllable non-deterministic stream X-machine
A stream X-machine is a type of extended finite state machine with an associated development approach that consists of building a system from a set of trusted components. One of th...
Robert M. Hierons, Florentin Ipate
DSN
2005
IEEE
14 years 1 months ago
Effective Testing and Debugging Techniques for a Group Communication System
View-oriented group communication is an important and widely used building block for constructing highlyavailable fault-tolerant systems. Unfortunately, groupcommunication based s...
Eitan Farchi, Gabriel Kliot, Yoel Krasny, Alex Kri...
ICSE
2005
IEEE-ACM
14 years 7 months ago
Testing database transactions with AGENDA
AGENDA is a tool set for testing relational database applications. An earlier prototype was targeted to applications consisting of a single query and included components for popul...
Yuetang Deng, Phyllis G. Frankl, David Chays