With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage ...
Salvador Petit, Julio Sahuquillo, Jose M. Such, Da...
Information networks are ubiquitous in many applications and analysis on such networks has attracted significant attention in the academic communities. One of the most important ...
This paper describes an inter-procedural technique for computing symbolic bounds on the number of statements a procedure executes in terms of its scalar inputs and user-defined qu...
Sumit Gulwani, Krishna K. Mehra, Trishul M. Chilim...