306 search results - page 22 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
FPGA
2009
ACM
14 years 4 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...