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DAC
2012
ACM
11 years 10 months ago
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
IPPS
2010
IEEE
13 years 5 months ago
MMT: Exploiting fine-grained parallelism in dynamic memory management
Dynamic memory management is one of the most expensive but ubiquitous operations in many C/C++ applications. Additional features such as security checks, while desirable, further w...
Devesh Tiwari, Sanghoon Lee, James Tuck, Yan Solih...
ECRTS
2007
IEEE
14 years 2 months ago
Memory Resource Management for Real-Time Systems
Dynamic memory storage has been widely used for years in computer science. However, its use in real-time systems has not been considered as an important issue, and memory manageme...
Audrey Marchand, Patricia Balbastre, Ismael Ripoll...
IPPS
1996
IEEE
13 years 11 months ago
A Virtual Memory Model for Parallel Supercomputers
A model for virtual memory in a distributed memory parallel computer is proposed. It uses a novel parallel computing operating system framework and leads to the definition of two ...
Veronica L. M. Reis, Isaac D. Scherson