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HIPEAC
2009
Springer
14 years 20 days ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
13 years 15 days ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...
CLUSTER
2009
IEEE
13 years 6 months ago
Coordinating the use of GPU and CPU for improving performance of compute intensive applications
GPUs have recently evolved into very fast parallel co-processors capable of executing general purpose computations extremely efficiently. At the same time, multi-core CPUs evolutio...
George Teodoro, Rafael Sachetto Oliveira, Olcay Se...
SIPS
2008
IEEE
14 years 3 months ago
The support of software design patterns for streaming RPC on embedded multicore processors
The development of embedded system has been toward the multicore architectures in the recent years. It raises concerns in the community of supporting programming models and langua...
Kun-Yuan Hsieh, Yen-Chih Liu, Chi-Hua Lai, Jenq Ku...
EUROPAR
2009
Springer
14 years 1 months ago
Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
Cédric Augonnet, Samuel Thibault, Raymond N...