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» Structural In-Field Diagnosis for Random Logic Circuits
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ET
2006
98views more  ET 2006»
13 years 7 months ago
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
1 Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of the...
Yu-Chiun Lin, Shi-Yu Huang
TCAD
2002
121views more  TCAD 2002»
13 years 7 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
ISPD
2012
ACM
289views Hardware» more  ISPD 2012»
12 years 3 months ago
Keep it straight: teaching placement how to better handle designs with datapaths
As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell com...
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanat...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 1 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 12 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor