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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 5 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...
97
Voted
ACMSE
2006
ACM
15 years 8 months ago
Using genetic algorithms to generate test plans for functionality testing
Like in other fields, computer products (applications, hardware, etc.), before being marketed, require some level of testing to verify whether they meet their design and function...
Francisca Emanuelle Vieira, Francisco Martins, Raf...
94
Voted
AIME
2001
Springer
15 years 6 months ago
A User Interface for Executing Asbru Plans
Asbru is a language for specifying treatment plans. These plans are then used by an execution unit to give advice to the medical staff what actions to take (open-loop system). In ...
Robert Kosara, Silvia Miksch
MEMOCODE
2010
IEEE
15 years 6 days ago
A formal executable semantics of Verilog
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
Patrick O'Neil Meredith, Michael Katelman, Jos&eac...
ASE
2004
148views more  ASE 2004»
15 years 2 months ago
TestEra: Specification-Based Testing of Java Programs Using SAT
TestEra is a framework for automated specification-based testing of Java programs. TestEra requires as input a Java method (in sourcecode or bytecode), a formal specification of th...
Sarfraz Khurshid, Darko Marinov