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MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 5 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
HIPC
2009
Springer
13 years 5 months ago
Fast checkpointing by Write Aggregation with Dynamic Buffer and Interleaving on multicore architecture
Large scale compute clusters continue to grow to ever-increasing proportions. However, as clusters and applications continue to grow, the Mean Time Between Failures (MTBF) has redu...
Xiangyong Ouyang, Karthik Gopalakrishnan, Tejus Ga...
CSE
2011
IEEE
12 years 7 months ago
Parallel Execution of AES-CTR Algorithm Using Extended Block Size
—Data encryption and decryption are common operations in a network based application programs with security. In order to keep pace with the input data rate in such applications, ...
Nhat-Phuong Tran, Myungho Lee, Sugwon Hong, Seung-...
CPHYSICS
2010
135views more  CPHYSICS 2010»
13 years 7 months ago
An events based algorithm for distributing concurrent tasks on multi-core architectures
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
David W. Holmes, John R. Williams, Peter Tilke
PDP
2011
IEEE
12 years 11 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...