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EGH
2004
Springer
13 years 11 months ago
Efficient partitioning of fragment shaders for multiple-output hardware
Partitioning fragment shaders into multiple rendering passes is an effective technique for virtualizing shading resource limits in graphics hardware. The Recursive Dominator Split...
Tim Foley, Mike Houston, Pat Hanrahan
WSCG
2004
161views more  WSCG 2004»
13 years 9 months ago
Rendering Techniques for Hardware-Accelerated Image-Based CSG
Image-based CSG rendering algorithms for standard graphics hardware rely on multipass rendering that includes reading and writing large amounts of pixel data from and to the frame...
Florian Kirsch, Jürgen Döllner
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
14 years 1 months ago
Transition time bounded low-power clock tree construction
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...
Min Pan, Chris C. N. Chu, J. Morris Chang
BIBM
2010
IEEE
139views Bioinformatics» more  BIBM 2010»
13 years 5 months ago
Scalable, updatable predictive models for sequence data
The emergence of data rich domains has led to an exponential growth in the size and number of data repositories, offering exciting opportunities to learn from the data using machin...
Neeraj Koul, Ngot Bui, Vasant Honavar
ICCAD
2007
IEEE
140views Hardware» more  ICCAD 2007»
14 years 4 months ago
Thermal-aware Steiner routing for 3D stacked ICs
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
Mohit Pathak, Sung Kyu Lim