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ISHPC
1999
Springer
13 years 12 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
HIPEAC
2010
Springer
13 years 9 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...
IPPS
2007
IEEE
14 years 1 months ago
A Utility-based Approach to Cost-Aware Caching in Heterogeneous Storage Systems
Modern single and multi-processor computer systems incorporate, either directly or through a LAN, a number of storage devices with diverse performance characteristics. These stora...
Liton Chakraborty, Ajit Singh
TPDS
2010
125views more  TPDS 2010»
13 years 2 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
14 years 1 months ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...